`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:51:04 11/19/2020 
// Design Name: 
// Module Name:    DM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DM(
	 input [31:0] WPC,
    input [11:0] memAddr,
    input [31:0] RD2,
    input memWrite,
    input clk,
    input reset,
    output [31:0] memData
    );
	 integer i;
	 reg [7:0]ram[8191:0];
	 wire [31:0]memAddress;
	 assign memAddress = {{20{0}},memAddr};
	 
	 always @(posedge clk)
	 begin
		if(reset)
		begin
			for(i = 0;i < 8192;i = i + 1)
				ram[i]<=0;
		end
		else begin
			if (memWrite)
			begin
				ram[memAddr] <= RD2[31:24];
				ram[memAddr+1] <= RD2[23:16];
				ram[memAddr+2] <= RD2[15:8];
				ram[memAddr+3] <= RD2[7:0];
				$display("@%h: *%h <= %h", WPC, memAddress, RD2);
			end		
		end
	 end
	 
	assign memData = {ram[memAddr][7:0],ram[memAddr+1][7:0],ram[memAddr+2][7:0],ram[memAddr+3][7:0]};

endmodule
